Putting hardware accelerators to work with automatic code translation

By | April 3, 2020
illustration of computer chip
(The Michigan Engineer)

Most programs in use today have to be completely rewritten at a very low level to reap the benefits of hardware acceleration. This system demonstrates how to make that translation automatic. A new technique developed by researchers at U-M could enable broader adoption of post-Moore’s Law computing components through automatic code translation.

The system, called AutomataSynth, allows software engineers to tap into the power of hardware accelerators like field-programmable gate array (FPGAs) without specialized programming knowledge or needing to rewrite old, CPU-centric code. FPGAs can be dedicated to rapidly executing particular common functions and eliminating bottlenecks in larger applications.