Taking transistor arrays into the third dimension

By | November 21, 2019
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An illustration of a step in the production process, injecting the zinc-tin-solution atop the spinning silicon chip. (Youngbae Son and Rose Anderson, Peterson Lab)

Silicon integrated circuits, which are used in computer processors, are approaching the maximum feasible density of transistors on a single chip—at least, in two-dimensional arrays. Now, a team of engineers at U-M have stacked a second layer of transistors directly atop a state-of-the-art silicon chip.

They propose that their design could remove the need for a second chip that converts between high- and-low voltage signals, which currently stands between the low-voltage processing chips and the higher-voltage user interfaces. “Our approach can achieve better performance in a smaller, lighter package,” said Becky Peterson, an associate professor of electrical engineering and computer science and project leader.